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sy89859u precision low - power 8:1 mux with internal termination and 1:2 lvpecl fanout buffer precision edge is a regis tered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 08 00 ? fax + 1 (408) 474- 1000 ? http://www.micrel.com december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89859u is a low jitter, low - power, high - speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. the sy89859u distributes clock frequencies from dc to >2.5ghz, and data rates to 2.5gbps guaranteed over temperature and voltage. the sy89859u differential input includes micrel?s unique, 3 - pin input termination architecture that directly interfaces to any differential signal (ac - or dc- coupled) as sma ll as 100mv (200mvpp) without level shifting or termination resistor networks in the signal path. the outputs are 800mv, 100k - compatible lvpecl with extremely fast rise/fall time guaranteed to be less than 180ps. the sy89859u features a patent - pending isol ation design that significantly improves on channel - to - channel crosstalk - induced jitter performance. the sy89859u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of ? 40c to +85c. the sy89859u is p art of micrel?s high - speed, precision edge ? product line. all support documentation can be found on m i crel?s web site at: www.micrel.com . precision edge ? features ? selects between 1 of 8 inputs, and provides 2 pr ecision, low skew 100k - compatible lvpecl output copies ? low power: 150mw typ. (2.5v) ? guaranteed ac performance over temperature and voltage: ? dc to >2.5gbps ? dc to >2.5ghz ? <690ps propagation delay ? <180ps t r /t f time ? <20ps skew (output - to - output) ? u nique, patent - pending channel - to - channel isolation design provides superior crosstalk performance ? ultra - low jitter design: ? <1ps rms random jitter ? <10ps pp deterministic jitter ? <10ps pp total jitter (clock) ? <1ps rms cycle - to - cycle jitter ? <0.7ps rms crosstalk - induced jitter ? unique, patented input termination and vt pin accepts dc - and ac - coupled inputs (cml, pecl, lvds) ? power supply 2.5v 5% or 3.3v 10% ? ? 40c to +85c industrial temperature range ? available in 44 - pin (7mm x 7mm) qfn package applicati ons ? data communication systems ? all sonet/sdh data/clock applications ? all fibre channel applications ? all gigabit ethernet applications
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 2 functional block diagram
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 3 ordering information (1) part number package type operating range package marking lead fini sh sy89859umy qfn -44 indu s trial sy89859u with pb - free bar - line indicator matte -sn pb - free sy89859umy tr (2) qfn -44 indu s trial sy89859u with pb - free bar - line indicator matte -sn pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44- pin qfn truth table sel2 sel1 sel0 q /q l l l in0 /in0 l l h in1 /in1 l h l in2 /in2 l h h in3 /in3 h l l in4 /in4 h l h in5 /in5 h h l in6 /in6 h h h in7 /in7
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 4 pin des cription pin number pin name pin function 20, 18 16, 14 13, 11 9, 7 5, 3 1, 43 42, 40 38, 36 in0, /in0 in1, /in1 in2, /in2 in3, /in3 in4, /in4 in5, /in5 in6, /in6 in7, /in7 differential inputs: these input pairs are the differential signal inputs to the device. inputs accept ac - or dc - coupled signals as small as 100mv (200mvpp). each pin of a pair internally terminates to a vt pin through 50 ?. note that these inputs will default to an indeterminate state if left open. please refer to the ?input interface applications? section for more details. 19, 15 12, 8 4, 44 41, 37 vt0, vt1 vt2, vt3 vt4, vt5 vt6, vt7 input termination center - tap: each side of the differential input pair terminates to a vt pin. the vt pins provide a center - tap to a termination network for maximum interface flexibility. see ?input interface applications? section for more details. for a cml or lvds inputs, the vt pin is left floating. 17 10 2 39 vref - ac0 vref - ac1 vref - ac2 vref - ac3 reference voltage: these outputs bias to v cc ? 1.2v. they are used when ac coupling the inputs (in, /in). for ac - coupled applications, connect vref - ac to the vt pin and bypass with a 0.01f low esr capacitor to vcc. see ?input interface applications? section for more details. 21 22 35 sel0 sel1 sel2 the singl e - ended ttl/cmos - compatible inputs select the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. the threshold voltage is v th = v cc /2. 24, 27, 29, 32 vcc positive power supply. bypass with 0.1f||0.01f low esr capacitors and place as close to each vcc pin as possible. 25, 26 30, 31 q0, /q0 q1, /q1 differential outputs: these 100k - compatible lvpecl output pairs are the outputs of the device. unused output pairs may be left open. each output is designed to drive 800mv into 50 ? terminated to v cc ? 2v. 23, 28, 33 gnd exposed pad ground. gnd and exposed pad must both be connected to the same ground plane.
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 5 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5 v to +4.0v input voltage sel0, sel1, sel2 .......................... ? 0.5v to v cc in0, /in0, in1, /in1,?/in7, /in7 ...... ? 0.5v to v cc lvpecl output current (i out ) continuous ................................................ 50ma surge ...................................................... 100ma termination current source or sink current vt0, vt1, vt2,?vt7 ............................. 100ma input current source or sink current in0, /in0, in1, /in1,?in7, /in7 ................ 50ma vref output current vref - ac0, vref - ac1?, vref - ac3 ....... 2ma lead temperature (soldering, 20 sec.) .......... +260c storage temperature (t s ) ................. ? 65c to 150c operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ................................................. +3.0v to +3.6v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) qfn ( ja ) still - air ................................................ 24c/w qfn ( jb ) junction - to - board ............................... 12c/w dc electrical characteristics (4) t a = ? 40c to +85c, unless otherwise stated. symbol parameter cond ition min typ max units v cc power supply 2.375 2.5 2.625 v 3.0 3.3 3.6 v i cc power supply current no load, max. v cc 60 85 ma r in input resistance (in -to -v t ) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input h igh voltage (in, /in) note 5 v cc ? 1.6 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 1a. 0.1 1.7 v v diff_in differential input voltage swing |in -to - /in| see figure 1b. 0.2 v v t_in in -to -v t (in, /in) 1.28 v v ref - ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and fun c tional operation is not implied at conditions other than tho se detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still - air, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 5. v ih (min) not lower than 1.2v.
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 6 100k lvpecl output dc electrical characteristics (6) v cc = +2.5v 5% or 3.3v 10%, r l = 50 ? to v cc ? 2v; t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage (q, /q) v cc ? 1.145 v cc ? 0.895 v v ol outpu t low voltage (q, /q) v cc ? 1.945 v cc ? 1.695 v v out output differential swing see figure 1a. 550 800 mv v diff_out differential output voltage swing see figure 1b. 1100 1600 mv lvttl/cmos dc electrical characteristics (6) v cc = +2.5v 5% or 3.3v 10%; t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current i ih @ v in = v cc ? 125 40 a i il input low current i il @ v in = 0.5v ? 300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 7 ac electrical characteristics (7) v cc = +2.5v 5% or 3.3v 10%; v in 100mv (200mvpp); r l = 50 ? to v cc ? 2v; t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency 2.5 gbps 2.5 3.5 ghz t pd differential propagation delay in -to -q sel -to -q 360 475 640 ps 200 600 850 ps t pd tempco differential propagation delay te m perature coefficient in -to -q 300 fs/ o c sel -to -q 400 t skew output -to - output skew note 8 5 20 ps part -to - part skew note 9 200 ps t jitter data random jitter (rj) note 10 1 ps rms deterministic jitter (dj) note 11 10 ps pp clock cycle -to - cycle jitter note 12 1 ps rms total jitter (tj) note 13 10 ps pp adjacent channel crosstalk - induced jitter note 14 0.7 ps rms t r, t f output rise/fall tim e (20% to 80%) at full output swing. 50 110 180 ps notes: 7. high - frequency ac - parameters are guaranteed by design and characterization. 8. output - to - output skew is measured between two different outputs under identical input transitions. 9. part - to - part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. random jitter is measured with a k28.7 character pattern, measured at micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 8 typical operating characteristics v cc = 3.3v, gnd = 0, v in = 100mv (200mvpp), r l = 50 ? to v cc ? 2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 9 functional characteristics v cc = 3.3v, gnd = 0, v in = 100mv (200mvpp), r l = 5 0 ? to v cc ? 2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 10 input and output stages figure 2a. simplified differential input stage figure 2b. simplified lvpecl output stage input interface applications figure 3a. lvpecl interface (dc - coupl ed) figure 3b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 3c. cml interface (dc - coupled) figure 3d. cml interface (ac - coupled) figure 3e. lvds interface
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 11 lvpecl output interface applications lvpecl has high inpu t impedance, very low output (open emitter) impedance, and small signal swing which result in low emi. lvpecl is ideal for driving 50? - and 100 ? - controlled impedance transmission lines. there are several techniques for terminating the lvpecl output including: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unused output pairs m ay be left floating. however, single - ended outputs must be terminated, or balanced. figure 4a. parallel thevenin - equivalent termination note: for 2.5v system, r1 = 250 ?, r2 = 62.5?. figure 4b. parallel termination (3 - resistor) note: for 2.5v system, rb = 19 ?. related product and support documentation part number function data sheet link sy58037u ultra precision 8:1 mux with internal termination and 1:2 cml fanout buffer http://www.micrel.com/product - info/products/sy58037u.shtml sy58038u ultra precision 8:1 mux with internal termination and 1:2 lvpecl fanout buffer http://www.micrel.com/product - info/products/sy58038u.shtml sy58039u ultra precision 8:1 mux with internal termination and 1:2 400mv lvpecl fanout buffer http://www.micrel.com/pro duct - info/products/sy58039u.shtml hbw solutions new products and applications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 12 package information 44- pin qfn ( qfn -44) pcb thermal consideration for 44 - pin qfn ? package (always solder, or equivalent, the exposed pad to the pcb) package notes: 1. package meets level 2 qualification. 2. all parts are dry - packaged before shipment. 3. exposed pads must be soldered to a ground fo r proper thermal management.
micrel, inc. sy89859u december 2007 m9999- 120607-d hbwhelp@micrel.com or (408) 955 -1 690 13 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. howe ver, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life suppor t appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or susta in life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchas er?s own risk and purchaser agre es to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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